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PSoC(R) Mixed-Signal Array
CY8C20234 CY8C20334 and CY8C20434
Final Data Sheet
Features
Low Power CapSense Block Configurable Capacitive Sensing Elements Supports Combination of CapSense Buttons, Sliders, Touchpads and Proximity Sensors Powerful Harvard Architecture Processor M8C Processor Speeds Running up to 12 MHz Low Power at High Speed 2.4V to 5.25V Operating Voltage Industrial Temperature Range: -40C to +85C Complete Development Tools Free Development Tool (PSoC DesignerTM) Full-Featured, In-Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Trace Memory Precision, Programmable Clocking Internal 5.0% 6/12 MHz Main Oscillator Internal Low Speed Oscillator at 32 kHz for Watchdog and Sleep Programmable Pin Configurations Pull Up, High Z, Open Drain, CMOS Drive Modes on All GPIO Up to 28 Analog Inputs on GPIO Configurable Inputs on All GPIO Selectable, Regulated Digital IO on Port 1 -- 3.0V, 20 mA Total Port 1 Source Current -- 5 mA Strong Drive Mode on Port 1 Versatile Analog Mux Common Internal Analog Bus Simultaneous Connection of IO Combinations Comparator Noise Immunity Low-Dropout Voltage Regulator for the Analog Array
Additional System Resources Configurable Communication Speeds -- I2C: Selectable to 50 kHz, 100 kHz or 400 kHz -- SPI : Configurable between 46.9 kHz and 3 MHz I2CTM Slave SPI Master and SPI Slave Watchdog and Sleep Timers Internal Voltage Reference Integrated Supervisory Circuit
Flexible On-Chip Memory 8K Flash Program Storage 50,000 Erase/Write Cycles 512 Bytes SRAM Data Storage Partial Flash Updates Flexible Protection Modes Interrupt Controller In-System Serial Programming (ISSP)
PSoC(R) Functional Overview
The PSoC family consists of many Mixed-Signal Array with OnChip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable component. A PSoC device includes configurable analog and digital blocks, as well as programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts. The PSoC architecture for this device family, as illustrated on the left, is comprised of three main areas: the Core, the System Resources, and the CapSense Analog System. A common, versatile bus allows connection between IO and the analog system. Each CY8C20x34 PSoC device includes a dedicated CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. Depending on the PSoC package, up to 28 general purpose IO (GPIO) are also included. The GPIO provide access to the MCU and analog mux.
September 18, 2006 (c) Cypress Semiconductor Corp. 2005-2006 -- Document No. 001-05356 Rev. *B
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PSoC(R) Overview
The PSoC Core
The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO (internal main oscillator) and ILO (internal low speed oscillator). The CPU core, called the M8C, is a powerful processor with speeds up to 12 MHz. The M8C is a two-MIPS, 8-bit Harvard architecture microprocessor. System Resources provide additional capability, such as a configurable I2C slave/SPI master-slave communication interface and various system resets supported by the M8C. The Analog System is composed of the CapSense PSoC block and an internal 1.8V analog reference, which together support capacitive sensing of up to 28 inputs.
The Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins can be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with the CapSense block comparator. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include:
Complex capacitive sensing interfaces, such as sliders and touchpads. Chip-wide mux that allows analog input from any IO pin. Crosspoint connection between any IO pin combinations.

The CapSense Analog System
The Analog System contains the capacitive sensing hardware. Several hardware algorithms are supported. This hardware performs capacitive sensing and scanning without requiring external components. Capacitive sensing is configurable on each GPIO pin. Scanning of enabled CapSense pins can be completed quickly and easily across multiple ports.
Additional System Resources
System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. Brief statements describing the merits of each system resource are presented below.
The I2C slave/SPI master-slave module provides 50/100/400 kHz communication over two wires. SPI communication over 3 or 4 wires runs at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock). Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.8V reference provides an absolute reference for capacitive sensing. The 5V maximum input, 3V fixed output, low-dropout regulator (LDO) provides regulation for IOs. A register-controlled bypass mode allows the user to disable the LDO.
IDAC
Analog Global Bus

Vr Reference Buffer
Cinternal
Comparator
Mux Mux
Refs
Cap Sense Counters
CSCLK IMO CapSense Clock Select Relaxation Oscillator (RO)
Analog System Block Diagram
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PSoC(R) Overview
Getting Started
The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, reference the PSoC Mixed-Signal Array Technical Reference Manual, which can be found on http://www.cypress.com/psoc. For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest PSoC device data sheets on the web at http://www.cypress.com.
Development Tools
PSoC Designer is a Microsoft(R) Windows-based, integrated development environment for the Programmable System-onChip (PSoC) devices. The PSoC Designer IDE and application runs on Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP. (Reference the PSoC Designer Functional Flow diagram below.) PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family.
Development Kits
Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items.
PSoC Designer
Graphical Designer Interface
Context Sensitive Help
Commands
Results
Technical Training
Free PSoC technical training is available for beginners and is taught by a marketing or application engineer over the phone. PSoC training classes cover designing, debugging, advanced analog, as well as application-specific classes covering topics such as PSoC and the LIN bus. Go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select Technical Training for more details.
Importable Design Database Device Database Application Database Project Database User Modules Library
Consultants
Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select CYPros Consultants.
PSoC Designer Core Engine
PSoC Configuration Sheet
Manufacturing Information File
Technical Support
PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm.
Emulation Pod In-Circuit Emulator Device Programmer
PSoC Designer Subsystems
Application Notes
A long list of application notes will assist you in every aspect of your design effort. To view the PSoC application notes, go to the http://www.cypress.com web site and select Application Notes under the Design Resources list located in the center of the web page. Application notes are sorted by date by default.
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PSoC(R) Overview
PSoC Designer Software Subsystems
Device Editor
The device editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration allows for changing configurations at run time. PSoC Designer sets up power-on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. Once the framework is generated, the user can add application-specific code to flesh out the framework. It's also possible to change the selected components and regenerate the framework.
Debugger
The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read the program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started.
Hardware Tools
In-Circuit Emulator
Application Editor
In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build. Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compiler. A C language compiler is available that supports the PSoC family of devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices. The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality.
A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation.
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PSoC(R) Overview
Designing with User Modules
The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk of having to select a different part to meet the final design requirements. To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called "User Modules." User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides highlevel functions to control and respond to hardware events at run time. The API also provides optional interrupt service routines that you can adapt as needed. The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. The development process starts when you open a new project and bring up the Device Editor, a graphical user interface (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the "Generate Application" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions.
Device Editor
User Module Selection Placement and Parameter -ization Source Code Generator
Generate Application
Application Editor
Project Manager Source Code Editor Build Manager
Build All
Debugger
Interface to ICE Storage Inspector Event & Breakpoint Manager
User Module and Source Code Development Flows The next step is to write your main program, and any sub-routines using PSoC Designer's Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive "grep-style" patterns. A single mouse click invokes the Build Manager. It employs a professional-strength "makefile" system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a HEX file image suitable for programming. The last step in the development process takes place inside the PSoC Designer's Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals.
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PSoC(R) Overview
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this document.
Acronym AC API CPU DC GPIO GUI ICE ILO IMO IO LSb LVD MSb POR PPOR PSoC(R) SLIMO SRAM alternating current application programming interface central processing unit direct current general purpose IO graphical user interface in-circuit emulator internal low speed oscillator internal main oscillator input/output least-significant bit low voltage detect most-significant bit power on reset precision power on reset Programmable System-on-ChipTM slow IMO static random access memory Description
Table of Contents
For an in depth discussion and more information on your PSoC device, obtain the PSoC Mixed-Signal Array Technical Reference Manual on http://www.cypress.com. This document is organized into the following chapters and sections.
1. Pin Information ..........................................................................7 1.1 Pinouts ..............................................................................7 1.1.1 16-Pin Part Pinout ...............................................7 1.1.2 24-Pin Part Pinout ...............................................8 1.1.3 32-Pin Part Pinout ...............................................9 1.1.4 48-Pin OCD Part Pinout .....................................10
2.
Electrical Specifications .........................................................11 2.1 Absolute Maximum Ratings .............................................12 2.2 Operating Temperature ...................................................12 2.3 DC Electrical Characteristics ...........................................12 2.3.1 DC Chip-Level Specifications .............................12 2.3.2 DC General Purpose IO Specifications ..............13 2.3.3 DC Analog Mux Bus Specifications ....................14 2.3.4 DC POR and LVD Specifications .......................14 2.3.5 DC Programming Specifications ........................15 2.4 AC Electrical Characteristics ...........................................16 2.4.1 AC Chip-Level Specifications .............................16 2.4.2 AC General Purpose IO Specifications ..............17 2.4.3 AC Comparator Amplifier Specifications ............18 2.4.4 AC Analog Mux Bus Specifications ....................18 2.4.5 AC External Clock Specifications .......................19 2.4.6 AC Programming Specifications .........................20 2.4.7 AC SPI Specifications ........................................21 2.4.8 AC I2C Specifications .........................................22 Packaging Information ...........................................................23 3.1 Packaging Dimensions ....................................................23 3.2 Thermal Impedances ......................................................27 3.3 Solder Reflow Peak Temperature ...................................27 Development Tool Selection ..................................................28 4.1 Software ..........................................................................28 4.1.1 PSoC Designer ...................................................28 4.1.2 PSoC Express ....................................................28 4.1.3 PSoC Programmer .............................................28 4.1.4 CY3202-C iMAGEcraft C Compiler ....................28 4.2 Development Kits ............................................................28 4.2.1 CY3215-DK Basic Development Kit ...................28 4.2.2 CY3210-ExpressDK Development Kit ................29 4.3 Evaluation Tools ..............................................................29 4.3.1 CY3210-MiniProg1 .............................................29 4.3.2 CY3210-PSoCEval1 ...........................................29 4.3.3 CY3214-PSoCEvalUSB .....................................29 4.4 Device Programmers .......................................................29 4.4.1 CY3216 Modular Programmer ...........................29 4.4.2 CY3207ISSP In-System Programmer ...............29 4.5 Accessories (Emulation and Programming) ....................30 4.6 3rd-Party Tools ................................................................30 4.7 Build a PSoC Emulator into Your Board ..........................30 Ordering Information ..............................................................31 5.1 Ordering Code Definitions ...............................................31 Sales and Service Information ...............................................32 6.1 Revision History ..............................................................32 6.2 Copyrights and Code Protection .....................................32
Units of Measure
A units of measure table is located in the Electrical Specifications section. Table 2-1 on page 11 lists all the abbreviations used to measure the PSoC devices.
3.
4.
Numeric Naming
Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexidecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (e.g., 01010100b' or `01000011b'). Numbers not indicated by an `h', `b', or 0x are decimal.
5. 6.
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1. Pin Information
This chapter describes, lists, and illustrates the CY8C20234, CY8C20334 and CY8C20434 PSoC device pins and pinout configurations.
1.1
Pinouts
The CY8C20x34 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a "P") is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, and XRES are not capable of Digital IO.
1.1.1
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CP IO IO IO IO
16-Pin Part Pinout
Type
Table 1-1. 16-Pin Part Pinout (QFN**)
Digital IO IO IOH IOH IOH IOH Power IOH IOH IOH Input I Power I I I Power I I I Analog I I I I I I Name P2[5] P2[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] XRES P0[4] Vdd P0[7] P0[3] P0[1] Vss Center pad must be connected to ground. Integrating input. Supply voltage. Optional external clock input (EXTCLK). Active high external reset with internal pull down. I2C SCL, SPI SS. I2C SDA, SPI MISO.
16 15
Description
CY8C20234 16-Pin PSoC Device
P0[1], AI AI, P2[5] AI, P2[1] AI, I2C SCL, SPI SS, P1[7] AI, I2C SDA, SPI MISO, P1[5] 1 2 P0[3], AI P0[7], AI Vdd 14 13 7 8 12 9 P0[4], AI XRES P1[4], AI, EXTCLK P1[2], AI CLK, I2C SCL, SPI MOSI P1[1] Vss AI, DATA, I2C SDA, P1[0]
SPI CLK. CLK*, I2C SCL, SPI MOSI. Ground connection. DATA*, I2C SDA.
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive. * These are the ISSP pins, which are not High Z at POR (Power On Reset). ** The center pad (CP) on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal.
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AI, SPI CLK, P1[3]
5 6
3 4
QFN (Top View) 11 10 CP
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1. Pin Information
1.1.2
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CP IO IO IO IO IO IO IO IO IO
24-Pin Part Pinout
Type
Table 1-2. 24-Pin Part Pinout (QFN**)
Digital IO IO IO IOH IOH IOH IOH Power IOH IOH IOH IOH Input I I I I I Power I I I I Power I I I I Analog I I I I I I I Name P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] NC Vss P1[0] P1[2] P1[4] P1[6] XRES P2[0] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] P0[1] Vss Center pad must be connected to ground. Integrating input. Analog bypass. Supply voltage. Active high external reset with internal pull down. Optional external clock input (EXTCLK). I2C SCL, SPI SS. I2C SDA, SPI MISO. SPI CLK. CLK*, I2C SCL, SPI MOSI. No connection. Ground connection. DATA*, I2C SDA. Description
CY8C20334 24-Pin PSoC Device
P0[1],AI P0[3],AI P0[5],AI P0[7],AI Vdd P0[6],AI AI,P2[5] AI,P2[3] AI,P2[1] AI, I2C SCL, SPI SS, P1[7] AI, I2C SDA, SPI MISO, P1[5] AI, SPI CLK, P1[3] 24 23 22 21 20 19
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details. ** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal.
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AI, CLK*, I2C SCL SPIMOSI,P1[1] 7 8 NC 9 Vss AI, DATA*, I2C SDA, P1[0] 10 AI,P1[2] 11 AI,EXTCLK,P1[4] 12
1 2 3 4 5 6
18 17 QFN 16 (Top View ) 15 14 13
P0[4],AI P0[2],AI P0[0],AI P2[0],AI XRES P1[6],AI
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1. Pin Information
1.1.3
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CP IO IO IO IO IO IO IO IO IO IO IO IO IO
32-Pin Part Pinout
Type
Table 1-3. 32-Pin Part Pinout (QFN**)
Digital IO IO IO IO IO IO IO IOH IOH IOH IOH Power IOH IOH IOH IOH Input I I I I I I I I I I Power I I I Power Power I I I I Analog I I I I I I I I I I I Name P0[1] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] Vss Vss Integrating input. Ground connection. Center pad must be connected to ground. Analog bypass. Supply voltage. Active high external reset with internal pull down. Optional external clock input (EXTCLK). I2C SCL, SPI SS. I2C SDA, SPI MISO. SPI CLK. CLK*, I2C SCL, SPI MOSI. Ground connection. DATA*, I2C SDA. Description
CY8C20434 32-Pin PSoC Device
AI,P0[1] AI,P2[7] AI,P2[5] AI,P2[3] AI,P2[1] AI,P3[3] AI,P3[1] SPISS,P1[7]
AI, I2C SCL
32 31 30 29 28 27 26 25
Vss P0[3],AI P0[5],AI P0[7],AI Vdd P0[6],AI P0[4],AI P0[2],AI 1 2 3 4 5 6 7 8
P2[7]
QFN
(Top View )
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive. * These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details. ** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal.
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AI, I2C SDA, SPI MISO, P1[5] AI, SPI CLK, P1[3] AI, CLK*, I2C SCL, SPI MOSI, P1[1] Vss AI, DATA*, I2C SDA, P1[0] AI,P1[2] AI,EXTCLK,P1[4] AI,P1[6]
9 10 11 12 13 14 15 16
24 23 22 21 20 19 18 17
P0[0],AI P2[6],AI P2[4],AI P2[2],AI P2[0],AI P3[2],AI P3[0],AI XRES
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1. Pin Information
1.1.4
48-Pin OCD Part Pinout
The 48-pin QFN part table and drawing below is for the CY8C20000 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production Table 1-4. 48-Pin OCD Part Pinout (QFN**)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 IO IO IO IO IO IOH IOH Input I I I I I I I IOH IOH I I IOH IOH Power I I IO IO IO IO IO IO IO IOH IOH I I I I I I I I I Analog Digital
CY8C20000 OCD PSoC Device
Name NC P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] NC NC NC NC P1[3] P1[1] Vss CCLK HCLK P1[0] P1[2] NC NC NC P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] Pin No. 41 42 43 44 No connection. No connection. No connection. Analog bypass. 45 46 47 48 CP Power IO IO IO Power I I I Analog Digital P2[4] Name Vdd OCDO OCDE P0[7] P0[5] P0[3] Vss NC Vss Integrating input. Ground connection. No connection. Center pad must be connected to ground. Supply voltage. OCD even data IO. OCD odd data output. Description Active high external reset with internal pull down. No connection. No connection. No connection. Optional external clock input (EXTCLK). I2C SCL, SPI SS. I2C SDA, SPI MISO. No connection. No connection. No connection. No connection. SPI CLK. CLK*, I2C SCL, SPI MOSI. Ground connection. OCD CPU clock output. OCD high speed clock output. DATA*, I2C SDA.
NC AI, P0[1] AI, P2[7] AI, P2[5] AI, P2[3] AI, P2[1] AI, P3[3] AI, P3[1] AI, I2C SCL, SPI SS, P1[7] AI, I2C SDA, SPI M ISO, P1[5] NC NC 1 2 3 4 5 6 7 8 9 10 11 12
Description
NC Vss P0[3],AI P0[5],AI P0[7],AI OCDE
No connection.
OCDO Vdd P0[6],AI NC
48 47 46 45 44 43
42 41 40
39 38 37
NC NC 36 35 34 33 32 31 30 29 28 27 26 25 P0[4], AI P0[2], AI P0[0], AI P2[6], AI P2[4], AI P2[2], AI P2[0], AI P3[2], AI P3[0], AI XRES P1[6], AI P1[4], EXT CLK, AI
OCD QFN
(Top V ie w )
13 14
15 16 17 18 19
20 21
AI,SPICLK,P1[3] AI,CLK*, I2CSCL, SPIMOSI,P1[1]
Not for Production
33 34 35 36 37 38 39 40
IO IO IO IO
I I I I
P2[6] P0[0] P0[2] P0[4] NC NC NC
Power
IO
I
P0[6]
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive. * ISSP pin which is not HighZ at POR. See the PSoC Mixed-Signal Array Technical Reference Manual for details. ** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal.
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Vss CCLK HCLK AI,DATA*,I2CSDA,P1[0] AI,P1[2] NC NC NC
NC NC
22 23 24
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2. Electrical Specifications
This chapter presents the DC and AC electrical specifications of the CY8C20234, CY8C20334 and CY8C20434 PSoC devices. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http:// www.cypress.com/psoc. Specifications are valid for -40oC TA 85oC and TJ 100oC as specified, except where noted. Refer to Table 2-10 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode.
5.25
5.25
SLIMO SLIMO SLIMO Mode=1 Mode=1 Mode=0
4.75 Vdd Voltage 4.75 Vdd Voltage
lid g Va ratin n pe io O Reg
3.60
SLIMO SLIMO Mode=1 Mode=0
3.00 2.70
3.00
SLIMO Mode=1
SLIMO Mode=0
2.40 750 kHz 3 MHz CPU Frequency 12 MHz
2.40 750 kHz 3 MHz 6 MHz 12 MHz
IMOFrequency
Figure 2-1a. Voltage versus CPU Frequency
Figure 2-1b. IMO Frequency Trim Options
The following table lists the units of measure that are used in this chapter. Table 2-1: Units of Measure
Symbol
oC
Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square
Symbol W mA ms mV nA ns nV pA pF pp ppm ps sps V microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak
Unit of Measure
dB fF Hz KB Kbit kHz k MHz M A F H s V Vrms
parts per million picosecond samples per second sigma: one standard deviation volts
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2. Electrical Specifications
2.1
Symbol TSTG
Absolute Maximum Ratings
Description Storage Temperature Min -55 25 Typ Max +100 Units
oC
Table 2-2. Absolute Maximum Ratings
Notes Higher storage temperatures will reduce data retention time. Recommended storage temperature is +25oC 25oC. Extended duration storage temperatures above 65oC will degrade reliability.
TA Vdd VIO VIOZ IMIO ESD LU
Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Electro Static Discharge Voltage Latch-up Current
-40 -0.5 Vss - 0.5 Vss - 0.5 -25 2000 -
- - - - - - -
+85 +6.0
oC
V
Vdd + 0.5 V Vdd + 0.5 V +50 - 200 mA V mA Human Body Model ESD.
2.2
Symbol TA TJ
Operating Temperature
Description Ambient Temperature Junction Temperature Min -40 -40 - - Typ Max +85 +100 Units
oC oC
Table 2-3. Operating Temperature
Notes The temperature rise from ambient to junction is package specific. See "Thermal Impedances" on page 27. The user must limit the power consumption to comply with this requirement.
2.3
2.3.1
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 2-4. DC Chip-Level Specifications
Symbol Vdd IDD12 IDD6 ISB27 ISB Supply Voltage Supply Current, IMO = 12 MHz Supply Current, IMO = 6 MHz Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Mid temperature range. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Description Min 2.40 - - - - - 1.5 1 2.6 2.8 Typ Max 5.25 2.5 1.5 4. 5 V mA mA A A Units Notes See table titled "DC POR and LVD Specifications" on page 14. Conditions are Vdd = 3.0V, TA = 25oC, CPU = 12 MHz. Conditions are Vdd = 3.0V, TA = 25oC, CPU = 6 MHz. Vdd = 2.55V, 0oC TA 40oC. Vdd = 3.3V, -40oC TA 85oC.
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2. Electrical Specifications
2.3.2
DC General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25C and are for design guidance only. Table 2-5. 5V and 3.3V DC GPIO Specifications
Symbol RPU VOH1 VOH2 VOH3 VOH4 VOH5 VOH6 VOL Pull-up Resistor High Output Voltage Port 0, 2, or 3 Pins High Output Voltage Port 0, 2, or 3 Pins High Output Voltage Port 1 Pins with LDO Regulator Disabled High Output Voltage Port 1 Pins with LDO Regulator Disabled High Output Voltage Port 1 Pins with LDO Regulator Enabled High Output Voltage Port 1 Pins with LDO Regulator Enabled Low Output Voltage Description 4 Vdd - 0.2 Vdd - 0.9 Vdd - 0.2 Vdd - 0.9 2.75 2.2 - Min - - - - 3.0 - - Typ 5.6 8 - - - - 3.2 - 0.75 Max V V V V V V V Units k IOH < 10 A, Vdd > 3.0V, maximum of 10 mA source current in all IOs. IOH = 1 mA, Vdd > 3.0V, maximum of 20 mA source current in all IOs. IOH < 10 A, Vdd > 3.0V, maximum of 10 mA source current in all IOs. IOH = 5 mA, Vdd > 3.0V, maximum of 20 mA source current in all IOs. IOH < 10 A, Vdd > 3.1V, maximum of 4 IOs all sourcing 5 mA. IOH = 5 mA, Vdd > 3.1V, maximum of 20 mA source current in all IOs. IOL = 20 mA, Vdd > 3V, maximum of 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5]). Vdd = 3.0 to 5.25. Vdd = 3.0 to 5.25. Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. Notes
VIL VIH VH IIL CIN COUT
Input Low Voltage Input High Voltage Input Hysteresis Voltage Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output
- 2.0 - - 0.5 0.5
- - 140 1 1.7 1.7
0.8 - - 5 5
V V mV nA pF pF
Table 2-6. 2.7V DC GPIO Specifications
Symbol RPU VOH1 VOH2 VOH3 VOH4 VOL Pull-up Resistor High Output Voltage Port 0, 2, or 3 Pins High Output Voltage Port 0, 2, or 3 Pins High Output Voltage Port 1 Pins with LDO Regulator Disabled High Output Voltage Port 1 Pins with LDO Regulator Disabled Low Output Voltage Description 4 Vdd - 0.2 Vdd - 0.5 Vdd - 0.2 Vdd - 0.5 - Min - - - - - Typ 5.6 8 - - - - 0.75 Max V V V V V Units k IOH < 10 A, maximum of 10 mA source current in all IOs. IOH = 0.2 mA, maximum of 10 mA source current in all IOs. IOH < 10 A, maximum of 10 mA source current in all IOs. IOH = 2 mA, maximum of 10 mA source current in all IOs. IOL = 10 mA, maximum of 30 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]). Vdd = 2.4 to 3.0V. Vdd = 2.4 to 3.0V. Gross tested to 1 A. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. Notes
VIL VIH VH IIL CIN COUT
Input Low Voltage Input High Voltage Input Hysteresis Voltage Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output
- 2.0 - - 0.5 0.5
- - 60 1 1.7 1.7
0.8 - - 5 5
V V mV nA pF pF
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2. Electrical Specifications
2.3.3
DC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 2-7. DC Analog Mux Bus Specifications
Symbol RSW Description Switch Resistance to Common Analog Bus - Min - Typ Max 400 800 Units Vdd 2.7V 2.4V Vdd 2.7V Notes
2.3.4
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 2-8. DC POR and LVD Specifications
Symbol VPPOR0 VPPOR1 VPPOR2 PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b 2.39 2.54 2.75 2.85 2.96 - - 4.52 2.45 2.71 2.92 3.02 3.13 - - 4.73 2.51a 2.78b 2.99c 3.09 3.20 - - 4.83 V V V V V V V V - Description Vdd Value for PPOR Trip 2.36 2.60 2.82 2.40 2.65 2.95 V V V Min Typ Max Units Notes Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog.
a. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply. b. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply. c. Always greater than 50 mV above VPPOR (PORLEV = 10) for falling supply.
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2. Electrical Specifications
2.3.5
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 2-9. DC Programming Specifications
Symbol VddIWRITE IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Description Supply Voltage for Flash Write Operations Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify Output Low Voltage During Programming or Verify Output High Voltage During Programming or Verify Flash Endurance (per block) Flash Endurance (total)a Flash Data Retention - - 2.2 - - - Vdd - 1.0 50,000 1,800,000 10 Min 2.70 - 5 - - - - - - - - - Typ - 25 0.8 - 0.2 1.5 Max V mA V V mA mA Driving internal pull-down resistor. Driving internal pull-down resistor. Units Notes
Vss + 0.75 V Vdd - - - V - - Years Erase/write cycles per block. Erase/write cycles.
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles).
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2. Electrical Specifications
2.4
2.4.1
AC Electrical Characteristics
AC Chip-Level Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 2-10. 5V and 3.3V AC Chip-Level Specifications
Symbol FCPU1 F32K1 FIMO12 Description CPU Frequency (3.3V Nominal) Internal Low Speed Oscillator Frequency Internal Main Oscillator Stability for 12 MHz (Commercial Temperature)a Internal Main Oscillator Stability for 6 MHz (Commercial Temperature) Duty Cycle of IMO Supply Ramp Time 15 11.4 Min 0.75 - 32 12 Typ 64 12.6 Max 12.6 Units MHz kHz MHz Trimmed for 3.3V operation using factory trim values. See Figure 2-1b, SLIMO Mode = 0. Trimmed for 3.3V operation using factory trim values. See Figure 2-1b, SLIMO Mode = 1. Notes 12 MHz only for SLIMO Mode = 0.
FIMO6
5.70
6.0
6.30
MHz
DCIMO TRAMP
40 0
50 -
60 -
% s
a. 0 to 70 C ambient, Vdd = 3.3 V.
Table 2-11. 2.7V AC Chip-Level Specifications
Symbol FCPU1 F32K1 FIMO12 Description CPU Frequency (2.7V Nominal) Internal Low Speed Oscillator Frequency Internal Main Oscillator Stability for 12 MHz (Commercial Temperature)a Internal Main Oscillator Stability for 6 MHz (Commercial Temperature) Duty Cycle of IMO Supply Ramp Time 8 11.0 Min 0.75 - 32 12 Typ 96 12.9 Max 3.25 Units MHz kHz MHz Trimmed for 2.7V operation using factory trim values. See Figure 2-1b, SLIMO Mode = 0. Trimmed for 2.7V operation using factory trim values. See Figure 2-1b, SLIMO Mode = 1. Notes
FIMO6
5.60
6.0
6.40
MHz
DCIMO TRAMP
40 0
50 -
60 -
% s
a. 0 to 70 C ambient, Vdd = 3.3 V.
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2. Electrical Specifications
2.4.2
AC General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 2-12. 5V and 3.3V AC GPIO Specifications
Symbol FGPIO TRise023 TRise1 TFall Description GPIO Operating Frequency Rise Time, Strong Mode, Cload = 50 pF Ports 0, 2, 3 Rise Time, Strong Mode, Cload = 50 pF Port 1 Fall Time, Strong Mode, Cload = 50 pF All Ports 0 15 10 10 Min - - - - Typ 6 80 50 50 Max Units MHz ns ns ns Notes Normal Strong Mode, Port 1. Vdd = 3.0 to 3.6V and 4.75V to 5.25V, 10% 90% Vdd = 3.0 to 3.6V, 10% - 90% Vdd = 3.0 to 3.6V and 4.75V to 5.25V, 10% 90%
Table 2-13. 2.7V AC GPIO Specifications
Symbol FGPIO TRise023 TRise1 TFall Description GPIO Operating Frequency Rise Time, Strong Mode, Cload = 50 pF Ports 0, 2, 3 Rise Time, Strong Mode, Cload = 50 pF Port 1 Fall Time, Strong Mode, Cload = 50 pF All Ports 0 15 10 10 Min - - - - Typ Max 1.5 100 70 70 Units MHz ns ns ns Notes Normal Strong Mode, Port 1. Vdd = 2.4 to 3.0V, 10% - 90% Vdd = 2.4 to 3.0V, 10% - 90% Vdd = 2.4 to 3.0V, 10% - 90%
90% GPIO Pin Output Voltage 10%
TRise023 TRise1
TFall
Figure 2-2. GPIO Timing Diagram
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2. Electrical Specifications
2.4.3
AC Comparator Amplifier Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 2-14. AC Operational Amplifier Specifications
Symbol TCOMP Description Comparator Response Time, 50 mV Overdrive Min Typ Max 100 200 Units ns ns Vdd 3.0V. 2.4V < Vcc < 3.0V. Notes
2.4.4
AC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 2-15. AC Analog Mux Bus Specifications
Symbol FSW Switch Rate Description - Min - Typ Max 3.17 Units MHz Notes
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2. Electrical Specifications
2.4.5
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 2-16. 5V AC External Clock Specifications
Symbol FOSCEXT - - - Frequency High Period Low Period Power Up IMO to Switch Description Min 0.750 38 38 150 - - - - Typ Max 12.6 5300 - - Units MHz ns ns s Notes
Table 2-17. 3.3V AC External Clock Specifications
Symbol FOSCEXT Description Frequency with CPU Clock divide by 1 Min 0.750 - Typ Max 12.6 Units MHz Notes Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
- - -
High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch
41.7 41.7 150
- - -
5300 - -
ns ns s
Table 2-18. 2.7V AC External Clock Specifications
Symbol FOSCEXT Description Frequency with CPU Clock divide by 1 Min 0.750 - Typ Max 3.080 Units MHz Notes Maximum CPU frequency is 3 MHz at 2.7V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. If the frequency of the external clock is greater than 3 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met.
FOSCEXT
Frequency with CPU Clock divide by 2 or greater
0.15
-
6.35
MHz
- - -
High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch
160 160 150
- - -
5300 - -
ns ns s
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2. Electrical Specifications
2.4.6
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 2-19. AC Programming Specifications
Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 TDSCLK2 Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Description 1 1 40 40 0 - - - - - Min - - - - - 15 30 - - - Typ 20 20 - - 8 - - 45 50 70 Max Units ns ns ns ns MHz ms ms ns ns ns 3.6 < Vdd 3.0 Vdd 3.6 2.4 Vdd 3.0 Notes
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2. Electrical Specifications
2.4.7
AC SPI Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 2-20. 5V and 3.3V AC SPI Specifications
Symbol FSPIM FSPIS TSS Description Maximum Input Clock Frequency Selection, Master Maximum Input Clock Frequency Selection, Slave Width of SS_ Negated Between Transmissions - - 50 Min - - - Typ Max 6.3 2.05 - Units MHz MHz ns Notes Output clock frequency is half of input clock rate.
Table 2-21. 2.7V AC SPI Specifications
Symbol FSPIM FSPIS TSS Description Maximum Input Clock Frequency Selection, Master Maximum Input Clock Frequency Selection, Slave Width of SS_ Negated Between Transmissions - - 50 Min - - - Typ Max 3.15 1.025 - Units MHz MHz ns Notes Output clock frequency is half of input clock rate.
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2. Electrical Specifications
2.4.8
AC I2C Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40C TA 85C, 3.0V to 3.6V and -40C TA 85C, or 2.4V to 3.0V and -40C TA 85C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25C and are for design guidance only. Table 2-22. AC Characteristics of the I2C SDA and SCL Pins for Vdd 3.0V
Standard Mode Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Set-up Time for STOP Condition Pulse Width of spikes are suppressed by the input filter. 0 4.0 4.7 4.0 4.7 0 250 4.0 - Min - - - - - - - - - Max 100 0 0.6 1.3 0.6 0.6 0 100a 0.6 1.3 0 Fast Mode Min - - - - - - - - 50 Max 400 Units kHz s s s s s ns s s ns Notes
Bus Free Time Between a STOP and START Condition 4.7
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Table 2-23. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported)
Standard Mode Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Set-up Time for STOP Condition Pulse Width of spikes are suppressed by the input filter. 0 4.0 4.7 4.0 4.7 0 250 4.0 - Min - - - - - - - - - Max 100 - - - - - - - - - - Fast Mode Min - - - - - - - - - - Max Units kHz s s s s s ns s s ns Notes
Bus Free Time Between a STOP and START Condition 4.7
SDA TLOWI2C TSUDATI2C THDSTAI2C
TSPI2C TBUFI2C
SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
Sr
P
S
Figure 2-3. Definition for Timing for Fast/Standard Mode on the I2C Bus
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3. Packaging Information
This chapter illustrates the packaging specifications for the CY8C20x34 PSoC device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161.
3.1
Packaging Dimensions
001-09116 **
Figure 3-1. 16-Lead (3x3 mm x 0.6 MAX) QFN -- Preliminary
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3. Packaging Information
001-09049 **
Figure 3-2. 24-Lead (4x4 x 0.6 mm) QFN -- Preliminary
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3. Packaging Information
001-06392 **
Figure 3-3. 32-Lead (5x5 mm 0.60 MAX) QFN
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3. Packaging Information
51-85152 *B
Figure 3-4. 48-Lead (7x7 mm) QFN
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
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3. Packaging Information
3.2
Thermal Impedances
Package 16 QFN** 24 QFN** 32 QFN** 48 QFN** Typical
Table 3-1. Thermal Impedances per Package JA *
46 oC/W 40 oC/W 27 oC/W 28 oC/W
* TJ = TA + Power x JA ** To achieve the thermal impedance specified for the ** package, the center thermal pad should be soldered to the PCB ground plane.
3.3
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability. Table 3-2. Solder Reflow Peak Temperature
Package 16 QFN 24 QFN 32 QFN 48 QFN Minimum Peak Temperature* 240 C 240oC 240oC 240oC
o
Maximum Peak Temperature 260oC 260oC 260oC 260oC
*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 5oC with Sn-Pb or 245 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
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4. Development Tool Selection
This chapter presents the development tools available for all current PSoC device families including the CY8C20x34 family.
4.1
4.1.1
Software
PSoC DesignerTM
4.2
Development Kits
All development kits can be purchased from the Cypress Online Store.
At the core of the PSoC development software suite is PSoC Designer. Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at http:// www.cypress.com under DESIGN RESOURCES >> Software and Drivers.
4.2.1
CY3215-DK Basic Development Kit
4.1.2
PSoC ExpressTM
The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the content of specific memory locations. Advance emulation features also supported through PSoC Designer. The kit includes:
PSoC Designer Software CD ICE-Cube In-Circuit Emulator ICE Flex-Pod for CY8C29x66 Family Cat-5 Adapter Mini-Eval Programming Board 110 ~ 240V Power Supply, Euro-Plug Adapter iMAGEcraft C Compiler (Registration Required) ISSP Cable USB 2.0 Cable and Blue Cat-5 Cable 2 CY8C29466-24PXI 28-PDIP Chip Samples
As the newest addition to the PSoC development software suite, PSoC Express is the first visual embedded system design tool that allows a user to create an entire PSoC project and generate a schematic, BOM, and data sheet without writing a single line of code. Users work directly with application objects such as LEDs, switches, sensors, and fans. PSoC Express is available free of charge at http://www.cypress.com/psocexpress.
4.1.3
PSoC Programmer
Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube InCircuit Emulator and PSoC MiniProg. PSoC programmer is available free ofcharge at http://www.cypress.com/psocprogrammer.
4.1.4
CY3202-C iMAGEcraft C Compiler
CY3202 is the optional upgrade to PSoC Designer that enables the iMAGEcraft C compiler. It can be purchased from the Cypress Online Store. At http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items..
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4. Development Tool Selection
4.2.2
CY3210-ExpressDK PSoC Express Development Kit
4.3.3
CY3214-PSoCEvalUSB
The CY3210-ExpressDK is for advanced prototyping and development with PSoC Express (may be used with ICE-Cube In-Circuit Emulator). It provides access to I2C buses, voltage reference, switches, upgradeable modules and more. The kit includes:
PSoC Express Software CD Express Development Board 4 Fan Modules 2 Proto Modules MiniProg In-System Serial Programmer MiniEval PCB Evaluation Board Jumper Wire Kit USB 2.0 Cable Serial Cable (DB9) 110 ~ 240V Power Supply, Euro-Plug Adapter 2 CY8C24423A-24PXI 28-PDIP Chip Samples 2 CY8C27443-24PXI 28-PDIP Chip Samples 2 CY8C29466-24PXI 28-PDIP Chip Samples
The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes:
PSoCEvalUSB Board LCD Module MIniProg Programming Unit Mini USB Cable PSoC Designer and Example Projects CD Getting Started Guide Wire Pack
4.4
Device Programmers
All device programmers can be purchased from the Cypress Online Store.
4.4.1
CY3216 Modular Programmer
4.3
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online Store.
The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes:
Modular Programmer Base 3 Programming Module Cards MiniProg Programming Unit PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
4.3.1
CY3210-MiniProg1
The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes:
MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
4.4.2
CY3207ISSP In-System Serial Programmer (ISSP)
4.3.2
CY3210-PSoCEval1
The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes:
CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240V Power Supply, Euro-Plug Adapter USB 2.0 Cable
The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:
Evaluation Board with LCD Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) PSoC Designer Software CD Getting Started Guide USB 2.0 Cable
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4. Development Tool Selection
4.5
Accessories (Emulation and Programming)
Pin Package 24 QFN 32 QFN Flex-Pod Kita CY325020334QFN CY325020434QFN Foot Kitb CY325024QFN-FK CY325032QFN-FK Prototyping Module CY32100X34 CY32100X34 Adapterc AS-24-2801ML-6 AS-32-2803ML-6
Table 4-1. Emulation and Programming Accessories
Part # CY8C20334 -12LFXI CY8C20434 -12LKXI
a. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. b. Foot kit includes surface mount feet that can be soldered to the target PCB. c. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com.
4.6
3rd-Party Tools
Several tools have been specially designed by the following 3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under DESIGN RESOURCES >> Evaluation Boards.
4.7
Build a PSoC Emulator into Your Board
For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see Application Note "Debugging - Build a PSoC Emulator into Your Board - AN2323" at http://www.cypress.com/ design/AN2323.
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5. Ordering Information
The following table lists the CY8C20234, CY8C20334 and CY8C20434 PSoC device's key package features and ordering codes. Table 5-1. PSoC Device Key Features and Ordering Information
CapSense Blocks XRES Pin Yes Yes Yes Yes Yes Yes Yes Digital IO Pins Ordering Code Package Analog Outputs 0 0 0 0 0 0 0 Inputs a Flash (Bytes) Analog SRAM (Bytes) Digital Blocks
16 Pin (3x3 mm 0.60 MAX) QFN 16 Pin (3x3 mm 0.60 MAX) QFN (Tape and Reel) 24 Pin (4x4 mm 0.60 MAX) QFN 24 Pin (4x4 mm 0.60 MAX) QFN (Tape and Reel) 32 Pin (5x5 mm 0.60 MAX) QFN 32 Pin (5x5 mm 0.60 MAX) QFN (Tape and Reel) 48 Pin OCD QFN
CY8C20234-12LKXI CY8C20234-12LKXIT CY8C20334-12LKXI CY8C20334-12LKXIT CY8C20434-12LKXI CY8C20434-12LKXIT CY8C20000-12LFXI
8K 8K 8K 8K 8K 8K 8K
512 512 512 512 512 512 512
0 0 0 0 0 0 0
1 1 1 1 1 1 1
13 13 20 20 28 28 28
13a 13a 20a 20a 28a 28a 28a
a. Dual-function Digital IO Pins also connect to the common analog mux.
5.1
Ordering Code Definitions
Package Type: PX = PDIP Pb-Free SX = SOIC Pb-Free PVX = SSOP Pb-Free LFX = QFN Pb-Free LKX = QFN Pb-Free AX = TQFP Pb-Free Speed: 12 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Thermal Rating: C = Commercial I = Industrial E = Extended
CY 8 C 20 xxx-12xx
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6. Sales and Service Information
To obtain information about Cypress Semiconductor or PSoC sales and technical support, reference the following information. Cypress Semiconductor 198 Champion Court San Jose, CA 95134 408.943.2600 Web Links: Company Information - http://www.cypress.com Sales - http://www.cypress.com/aboutus/sales_locations.cfm Technical Support - http://www.cypress.com/support/login.cfm
6.1
Revision History
Document Title: CY8C20234, CY8C20334, CY8C20434 PSoC(R) Mixed-Signal Array Final Data Sheet Document Number: 001-05356 Revision ECN # Issue Date Origin of Change Description of Change ** *A 404571 418513 See ECN See ECN HMT HMT New silicon and document (Revision **). Update Electrical Specs., including Storage Temperature and Maximum Input Clock Frequency. Update Features and Analog System Overview. Modify 32-pin QFN E-PAD dimensions. Add new 32-pin QFN. Add High Output Drive indicator to all P1[x] pinouts. Update trademarks. Make data sheet "Final." Add new Dev. Tool section. Add OCD pinout and package diagram. Add 16-pin QFN. Update 24- and 32-pin QFN package diagrams to 0.60 MAX thickness. Change from commercial to industrial temperature range. Update Storage Temperature specification and notes. Update thermal resistance data. Add dev. tool kit part numbers. Finetune features and electrical specs.
*B
490071
See ECN
HMT
Distribution: External/Public
Posting: None
6.2
Copyrights
Copyrights and Code Protection
(c) Cypress Semiconductor Corp. 2005-2006. All rights reserved. PSoC DesignerTM, Programmable System-on-ChipTM, and PSoC Express are trademarks and PSoC(R) is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. The information contained herein is subject to change without notice. Cypress Semiconductor assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress Semiconductor products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress Semiconductor. Flash Code Protection Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices. Cypress Semiconductor products meet the specifications contained in their particular data sheets. Cypress Semiconductor believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semiconductor, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress Semiconductor are committed to continuously improving the code protection features of our products.
September 18, 2006 (c) Cypress Semiconductor Corp. 2005-2006 -- Document No. 001-05356 Rev. *B
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